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microTech Global Ltd
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Northampton, Northamptonshire
Verification Manager
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Job Type: Full-time |
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Overview
JOB AD: We are a team of passionate professionals striving to make a mark in the trajectory of the semiconductor industry. If you love to be part of a start-up that is challenging established tech giants and you are a proactive problem-solver who is motivated by pushing your limits and challenging the status quo, we have an opportunity for you. We are actively seeking for a resourceful Digital Verification Manager for our office either in Northampton (UK) or Lausanne (CH). Key responsibilities - Build and manage a team of AMS and Digital Verification Engineers - responsibility for hiring, resourcing, scheduling, upskilling, mentoring, performance reviews, reporting and execution - Develop verification methodologies and compute infrastructure to meet the ever-increasing demand of verifying complex designs - Work closely with architecture, analog, and digital design teams to identify gaps in the design and/or design-flows. Implement improvement actions and ensure the delivery of high-quality designs - Be the verification technical authority during sign-off meetings, both at chip and IP level Your profile - 10 years' experience in the semiconductor industry, with min. 3 yrs in a verification leadership role (leading teams in different location an asset) - Proven track record in verifying complex designs (preferably in high volume applications) - Skilled in trade-offs between quality and schedule - Knowledge of product development life cycle and representing the verification discipline at project gate sign-off, incl- tape-out - Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debug skills - Bachelor of Engineering in Electronics and Electrical Engineering (equivalent or higher) Competencies - Must possess strong communication skills and demonstrated team building, leadership skills across sites - Deep understanding of verification planning and testbench development using the latest methodologies - Deep understanding of mixed-signal verification and building/correlating AMS models - Developing directed/constraint-random test generation (UVM), GLS, coverage analysis, and closure - Developing continuous-integration tests, regression debug support and other flow/infrastructure development - Proficient in System Verilog, Verilog A/MS and scripting languages (e.g. phyton, Perl, Tcl) - Experience with 3rd party VIP usage and test development - Experience in the latest verification methodologies, incl. property verification using formal methods - Experience with Cadence suite of analog and digital simulators - Knowledge of digital and analog design flows - Strong knowledge of SerDes and high-level protocols (e.g. PCle, USB, DP) Eu citizens or Swiss nationals.